Research
Research
My research focuses on cryogenic CMOS and machine-learning-based compact modeling for semiconductor devices.
Thread 01
Cryogenic CMOS Characterization and Compact Modeling
This work covers device measurement, forward body biasing, and model validation using circuit-level simulations.
Thread 02
Machine Learning for Compact Modeling
The work includes neural-network device models and their integration into circuit-simulation workflows.
Neural-network compact modeling
Thread 03
Open to New Challenges
I am particularly interested in problems that connect experimental data, modeling, and practical circuit design.
Open to new research challenges
Support
Research environment
This work is conducted in the Shintani Lab at Kyoto Institute of Technology in collaboration with researchers working on device characterization, modeling, and circuit design.