Measuring and modeling silicon at cryogenic temperatures
I characterize bulk CMOS down to cryogenic temperatures and build compact models that stay accurate across temperature and bias — from building the measurement environment, to silicon-validated models, to machine-learning approaches for compact modeling.
01. Cryogenic CMOS Characterization & Compact Modeling
Cryogenic operation reshapes CMOS device behavior, and room-temperature models break down at deep-cryogenic temperatures. I characterize bulk CMOS down to cryogenic conditions and build compact models that stay accurate across a wide temperature and bias range.
To support this, I built our laboratory's cryogenic measurement environment from scratch and released PyVAR3, an open-source tool that automates cryogenic CMOS measurement.
02. Machine Learning for Compact Modeling
Neural networks can capture device behavior that is hard to express analytically, but training accuracy degrades across the wide dynamic range of transistor currents. I work on normalization and training techniques that keep neural compact models accurate from sub-threshold to strong inversion.
03. Next Questions
The next thread is still forming: new device data, better compact models, and ML methods that make cryogenic CMOS easier to design with.
Lab and collaboration
This research is carried out in the Shintani Laboratory at the Kyoto Institute of Technology, in collaboration with colleagues across cryogenic device characterization, compact modeling, and circuit design.